(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of patterning a polysilicon layer in the manufacture of an integrated circuit device.
(2) Description of the Prior Art
Polysilicon pattern definition remains a significant challenge in semiconductor manufacturing. The minimum width of the polysilicon layer determines the minimum transistor length of MOS technologies. Transistor switching speed and packing density depend heavily on the ability to reliably and repeatably manufacture transistors with very narrow polysilicon gates.
Referring now to FIG. 1, a cross-section of a partially completed prior art integrated circuit device is shown. A gate oxide layer 14 overlies a semiconductor substrate 10. A polysilicon layer 18 overlies the gate oxide layer 14. A hard mask layer 22 overlies the polysilicon layer 18. Finally, a photoresist layer 26 overlies the hard mask layer 22. Note that the photoresist layer 26 has been patterned by, for example, a photolithographic sequence of coating, exposure, and development.
Referring now to FIG. 7, the polysilicon layer 18 is patterned using the prior art sequence that is illustrated by the process flow chart. Note, first, that the prior art process etches the pattern of the photoresist layer 26 into the hard mask layer 22 in step 30. Second, the photoresist layer 26 is stripped away in step 34. Third, the pattern of the hard mask layer 22 is etched into the polysilicon layer 18 in step 38. Finally, the hard mask layer 22 is stripped away in step 42. Note that an intervening resist strip (step 34) necessitates the removal of the wafers from the etching chamber between the hard mask etch (step 30) and the gate etch (step 38).
Referring now to FIG. 2 and to FIG. 7, step 30, the photoresist layer 26 may be trimmed. This trimming step is performed to reduce the width of the photoresist layer 26 to a dimension that is smaller than the capability of the photolithographic exposure equipment. This trimming etch is performed in the plasma dry etch chamber and reduces the width of the patterned photoresist layer 26 to a dimension that will enable the final patterned polysilicon layer 18 to meet the critical dimension (CD) specifications for the manufacturing process.
Referring now to FIG. 3 and to FIG. 7, step 30, the pattern of the photoresist layer 26 is etched into the hard mask layer 22. This etching step is again performed in the plasma dry etch chamber.
Referring now to FIG. 4 and to FIG. 7, step 34, the photoresist layer 26 is stripped away. This photoresist layer 26 must be removed to improve the selectivity of the plasma dry etch process. Because the gate oxide layer 14 of the deep sub-micron process is very thin, the subsequent polysilicon etching step must have a high selectivity to the gate oxide. Removing the photoresist layer 26 prior to the polysilicon etch step 38 improves this selectivity. This is the reason that the hard mask layer 22 is used.
Of particular importance to the present invention is the fact that the semiconductor wafers must be removed from the plasma dry etch chamber during photoresist stripping. A separate photoresist stripping chamber is typically used to strip away this remaining photoresist. Following the photoresist strip, the wafers are then returned to the plasma dry etch chamber for the gate or polysilicon layer 18 etch step 38. This polysilicon layer 18 is thereby etched in a photoresist free process that is herein called an ex-situ process.
The additional wafer handling and process equipment required to remove the photoresist layer 26 increases the cycle time and the processing cost. In addition, the wafers are open to increased contamination due to the handling and the additional processing chamber. The additional processing chamber also makes controlling processing parameters more difficult. Finally, additional inspections and CD measurement steps may be added to insure that the additional handling and process set-ups are within specification. This also adds to the processing cost and cycle time.
Referring now to FIG. 5 and to FIG. 7, step 38, the pattern of the hard mask layer 22 is etched into the polysilicon layer 18. This step is performed in the plasma dry etch chamber after the photoresist strip step 34.
Referring finally to FIG. 6 and to FIG. 7, step 42, the hard mask layer is stripped away to complete the patterning of the polysilicon layer 18. The wafers are removed from the plasma dry etch chamber for this processing step 42. The hard mask stripping may comprise a wet etch process.
Several prior art approaches disclose methods to pattern polysilicon in the manufacture to an integrated circuit device. U.S. Pat. No. 5,767,018 to Bell teaches a method to etch a polysilicon pattern where an anti-reflective coating (ARC) is used. Pitting problems are eliminated. In one embodiment, a passivation layer is formed on the sidewalls of the patterned ARC layer prior to polysilicon etching. In a second embodiment, the passivation layer is formed on the ARC layer sidewalls during the polysilicon etch. U.S. Pat. No. 6,037,266 to Tao et al discloses a method to etch a polysilicon pattern. A bottom anti-reflective coating (BARC) is used. The BARC layer and an oxide layer are etched to form a pattern over the polysilicon layer. The BARC layer is then stripped away using a biased O2 plasma. The polysilicon layer is then etched using the oxide layer as a hard mask. U.S. Pat. No. 5,346,586 to Keller teaches a method to etch a polysilicon pattern. A silicide layer is used overlying the polysilicon layer. An oxide layer overlies the silicide layer. The oxide layer is patterned using a hard mask layer. The photoresist layer is then removed using an ozone plasma strip. The silicide layer is etched. Finally, the polysilicon layer is etched. U.S. Pat. No. 5,885,902 to Blasingame et al discloses a method to etch an anti-reflective coating (ARC) layer using an inert gaseous plasma containing helium, nitrogen, or a mixture thereof.